Transmission or blocking gate



June 8, 1965 R. w. LA BAHN TRANSMISSION OR BLOCKING GATE Filed Sept. 25, 1962 RAYMOND W. LA BAHN INV EN TOR.

By zfif ATTORNEYS United States Patent 3,188,491 TRANSMISSION 0R BLOCKING GATE Raymond W. La Bahn, Orange, Califi, assignor to the United States of America as represented by the Secretary ofthe Navy Filed Sept. 25, 1962, Ser. No. 226,783 2 Claims. (Cl. 307-885) (Granted under Title 35, US. Code (1952), see. 266) The invention herein described may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties thereon or therefor.

. The present invention relates to a transmission or blocking gate circuit and more partciularly to a transmission or blocking gate which provides rapid control over the passage or blocking of electrical signals with a minimum of interaction between the controlling and gated signals.

Known devices for performing this function are the simple relay, diode gate and the pentode gate. The relay device provides good passage and blocking functions as well as minimum interaction between the controlling and gated signals but is very slow operating. The diodes provides fairly good passage and blocking functions and is capable of rapid operation but the control signal is also present on the output terminal, as well as the input terminal for AC. operation, resulting in large interaction between the gated and controlling signals. The pentode combines very good passage and blocking functions with very rapid operation but again, a large effect from the controlling signal is present on the output although not on the input.

Accordingly, an object of the present invention is the provision of an improved gatnig circuit.

Another object of the invention is to provide an im proved gating circuit which provides rapid switching with a minimum of interaction between the gating signal and the gated signal.

A further object of the invention is to provide for rapid switching and maintaining the zero reference level of AC. signals and amplification through the gate,

Other objects and many of the attendant advantages of this invention will become readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings wherein:

FIG. 1 shows a circuit diagram of a preferred embodiment of the invention, and

FIG. 2 shows a modification of the embodiment of FIG. 1.

Referring now to the drawings there is shown in FIG. 1 Schmidt trigger section coupled to a gating section 12. A positive DC. voltage is applied to terminal 14 while a negative DC. voltage of the same magnitude is applied to terminal 16. A control signal is applied at terminal .18 which is connected across input resistor to the base of transistor 22 having its collector connected to terminal 14 and its emitter connected through emitter resistor 24 and potentiometer 26 to terminal 16. The output of transistor 22 is coupled through capacitor 28 and potentiometer 26 to the ,base of transistor 30 which has its output coupled through RC network 32 to the base of transistor 34. The collectors of each of transistors 30 and 34 are respectively connected to terminal 14 through resistors 36 and 38 while their emitters are connected to terminal 16 through a common resistor 40. The base of transistor 34 is connected to terminal 16 through resistor 42. The output of the Schmidt trigger section 10 is coupled to the base of transistor 44 through variable RC network 46.

The output of section 10, which swings from near the negative voltage at terminal 16 to near the positive voltage at terminal 14, is used to saturate the gate controlling transistor 44, to turn the gate on or to turn the gate off when unsaturated. Transistor 44 is saturated when the collector of transistor 34 is near the maximum positive voltage at terminal 14 and is cut off when the collector of transistor 44 is near the maximum negative voltage at terminal 16. Trigger section 10 will operate in two ways which in turn will make gate 12 a transmission or a blocking gate. The conditions for obtaining one of these two modes of operation is controlled by the movable tap of potentiometer 26 which may be set to turn gate 12 on for a positive, going trigger input signal, gate 12 being normally in the off position (transmission gate open), or may be set to turn gate 12 off for a negative going trigger input signal, gate 12 being normally in the on position (blocking gate operation).

The output of transistor 44 is coupled by oppositely polarized diodes 43 and 48 respectively to the emitters of transistors 50 and 52. The collector of transistor 44 is connected through resistor 45 to terminal 14 while its emitter and base are respectively connected to terminal- 16 through resistors 47 and 49. The collector of transistor St) is connected through resistor 54 to terminal 14 and to the base of transistor 56 through variable RC network 58. The collector of transistor 52 is connected through resistor 53 to terminal 16 and to the base of transistor 56 through variable RC network 55.

The operation of gate 12, as controlled by the saturation or cutofi conditions of transistor 44 is as follows: When transistor 44 is saturated, its collector and emitter are both near ground potential. The bases of transistors 50 and 52, the gating transistors, are biased above ground potential by resistor combinations 63, and 69, 71 respec tively in such a way as to forward bias these transistors. Thus, by transistor action, the emitters of transistors 50 and 52 are also very near the same potential above ground. With transistor 44 saturated, this condition exists since diodes 43 and 48 are then in the backward biased condition and are essentially non-conducting. Transistors 50 and 56 act as amplifiers for any signals present at their bases since their collectors operate mid-way between the supply voltages and ground.

The signals applied at terminals 59 to be passed by gate 12 are imposed upon the bases of transistors 50 and 52 through coupling capacitors 60 and 62 respectively and appear amplified on the collectors Where they are summed through summing resistors 64 and 66 and imposed upon the base of transistor 56 which aifords an impedance transformation onto output terminal 68. Potentiometer 70 provides gate balance control by providing adjustment of the D0. levels of the collectors of transistors 50 and 52 to equal and opposite potentials while potentiometer 72 provides a DC. level adjust by inserting a slight positive bias into the base of transistor 56 such that the output D.C. level will be zero potential and thus the only output signal will be that imposed upon the bases of transistors 56 and 52 and amplified by them.

To turn the gate off, transistor 44 is cut off which allows its emitter and collector to approach the supply potentials. This in turn changes the bias conditions of diodes 43 and 48 from back to forward biased. This raises the emitter potentials of transistors 50 and 52 through resistors 45, 67 and resistors 47, 73 voltage divides combinations to a higher potential above ground than the base bias potentials determined by the resistor combinations 63, 65 and 69, '71 respectively, and thereby removes the forward bias currents through their base circuits. This essentially cuts off the collector currents of transistors 50 and52. allowing their collectors to go to supply potentials and making them inoperative. Thus, any signal imposed upon the base of transistors 50 and 52 will not be amplified or present upontheir collectors except for extremely small amounts which will be passed through the leakage resistance of transistors 50' and 52 respectively. Moreover, with equal and opposite supply potentials at terminals 14- and 16, the sum, of these currents flowing through resistors 54, 64 and 53, 66 will give no resulting D.C. shift on output terminal 68.

In operation the following values and components have been found to operate satisfactorily:

Terminal 14 potential +225 volts 11C, Terminal 16 potential ..225 volts D,C Transistors 22, 30, 34, 56 .2N697. Transistors 44, 50 -2N440. Transistors 52 2N404. Resistors 20, 24, 47, 69 .5.1K. Resistors 36,- 38' 2K. Resistor for RC network 32 .1.3K. Resistors for'RC network 46 22K. Resistor 4t) 30SZ. Resistor 42 M62052. Resisitor49 30K. Resistor 45 i .4.7K. Resistors 53, 54 7.5K. Resistors 67, 65, '71, 73 -JK.

Resistors 64, 66; .47K. Resistors 63, 69 11K. Resistor 71 100K. Resistor 73 .l meg. Potentiometer 26 10K. Potentiometer '70 "5009.

' Potentiometer '72 500K.

Capacitor 28 500 ,u f. Capacitor for RC network 32 .560 ,uuf. Capacitor for RC network 46, 55, 58 -4-40 [.L/Lf. Capacitors 60, 62' 0.033 t. Diodes 42, 48 .1N69A.

, In the modification shown in FIG! 2, a difierent type of transistor (2N404) is used and designated as '75. An additional resistor (30K), 76, has been added. Resistor 49 is eliminated. As shown in FIG. 2 the connection for the collector and emitter of transistor 75 are reversed from those of transistor 44 of FIG. 1. In this embodiment reverse action is obtained in that a positive going trigger input signal will turn off from a normally on condition or, a negative going trigger input signal will turn the gate on from a normally off condition.

Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.

What is claimed is:

1. In a gating circuit the combination comprising:

(a) a first transistor having a base, collector and an emitter,

(b) a Schmidt trigger generator for generating positive and negative control pulses,

(c) the base of said first transistor being coupled to the output of said Schmidt trigger generator,

(d) second and third transistors each having a base,

collector and emitter,

(e) resistor circuit means connecting the emitters of said second and third transistors,

(f) first rectifying means connected between the collector of said first transistor and. the emitter of said second transistor,

(g) second rectifying means being oppositely polarized to that of said first rectifyingmeans connected between the emitter of said. first transistor and the emitter of said third transistor,

(h) circuit means coupling an input'signal'tobe gated to the bases of said second and third transistors and (i) output circuit means coupled to the collectors of said second and third transistors. a

2. The gating circuit of claim 1 wherein said input signal circuit coupling means comprises:

(a) first and second capacitors connected in series between the bases of said second and third transistors,

(b) a first resistor connected between the base of said second transistor and a common junction,

(0) a second resistor connected between the base of said third transistor and'said common junction, and

(d) an input terminal connected intermediate said tirst and said series connected capacitors.

References Cited by the Examiner UNITED STATES PATENTS 2,864,961 12/58 Lehman et al 30788.5 2,910,597 10/59 Strong 307-885 2,956,175 10/60 BOthWell 30788.5 3,031,588 4/62 Hilsenrath 307-885 ARTHUR GAUSS, Primary Examiner. 

1. IN A GATING CIRCUIT THE COMBINATION COMPRISING: (A) A FIRST TRANSISTOR HAVING A BASE, COLLECTOR AND AN EMITTER, (B) A SCHMIDT TRIGGER GENERATOR FOR GENERATING POSITIVE AND NEGATIVE CONTROL PULSES, (C) THE BASE OF SAID FIRST TRANSISTOR BEING COUPLED TO THE OUTPUT OF SAID SCHMIDT TRIGGER GENERATOR, (D) SECOND AND THIRD TRANSISTORS EACH HAVING A BASE, COLLECTOR AND EMITTER, (E) RESISTOR CIRCUIT MEANS CONNECTING THE EMITTERS OF SAID SECOND AND THIRD TRANSISTORS, (F) FIRST RECTIFYING MEANS CONNECTED BETWEEN THE COLLECTOR OF SAID FIRST TRANSISTOR AND THE EMITTER OF SAID SECOND TRANSISTOR, (G) SECOND RECTIFYING MEANS BEING OPPOSITELY POLARIZED TO THAT OF SAID FIRST RECTIFYING MEANS CONNECTED BETWEEN THE EMITTER OF SAID FIRST TRANSISTOR AND THE EMITTER OF SAID THIRD TRANSISTOR, (H) CIRCUIT MEANS COUPLING AN INPUT SIGNAL TO BE GATED TO THE BASED OF SAID SECOND AND THIRD TRNSISTORS AND (I) OUTPUT CIRCUIT MEANS COUPLED TO THE COLLECTORS OF SAID SECOND AND THIRD TRANSISTORS. 